1. Field of the Invention
The present invention relates to a gain control circuit used in a car telephone, TV tuner and the like for controlling an input signal to a predetermined level and outputting the signal controlled to the predetermined level.
2. Description of the Related Art
FIG. 17 is a circuit diagram showing an example of the arrangement of a conventional gain control circuit, wherein reference character 1 designates an input terminal to which a high frequency signal voltage is input; reference character C.sub.1 designates a direct current check capacitor; reference character C.sub.2 designates a high frequency ground capacitor, reference characters Q.sub.1 and Q.sub.2 designate preamplifying transistors with similar characteristics; reference character 2 designates a constant voltage source for applying a bias voltage V.sub.1; reference characters R.sub.1 and R.sub.2 designate resistors for applying the bias voltage, respectively; reference characters R.sub.3 and R.sub.4 designate current feedback resistors, respectively; and reference character I.sub.1 designates a constant current source.
Further, reference character 3 designates a gain control voltage application terminal to which a gain control voltage is applied; reference characters 4 and 5 designate constant voltage sources for applying bias voltages V.sub.CC and V.sub.2, respectively; reference characters Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 designate gain control transistors with similar characteristics, respectively; reference characters R.sub.5 and R.sub.6 designate load resistors, respectively; and reference characters C.sub.3 and C.sub.4 designate direct current check capacitors, respectively. Then. the transistors Q.sub.3 -Q.sub.6 and load resistors R.sub.5 and R.sub.6 constitute a first gain control unit 6.
Further, reference characters Q.sub.7, Q.sub.8, Q.sub.9 and Q.sub.10 designate gain control transistors with similar characteristics, respectively; reference characters I.sub.2 and I.sub.3 designate constant current sources, respectively; reference characters R.sub.7 and R.sub.8 designate load resistors, respectively; reference character C.sub.5 designates a direct current check capacitor; and reference character 7 designates an output terminal from which a gain-controlled high Q.sub.10 and load resistors R.sub.7 and R.sub.8 constitute a second gain control unit 8.
In this arrangement, a gain control voltage is applied to the gain control voltage application terminal 3 based on the result of the detection of the signal voltage output from the gain control circuit and detected by a not shown circuit so that the signal voltage output from the gain control circuit is kept to a predetermined level.
First, when the gain of the gain control circuit is maximized (hereinafter, this is referred to as at the time of maximum gain), a voltage (V.sub.2 +.DELTA.V) (V) is applied to the gain control voltage application terminal 3 as the gain control voltage.
With this arrangement, the transistors Q.sub.3 and Q.sub.6 of the first gain control unit 6 and the transistors Q.sub.7 and Q.sub.10 of the second gain control unit 8 are turned ON, respectively and collector direct currents I.sub.C3, I.sub.C6, I.sub.C7 and I.sub.C10 flow to the respective transistors Q.sub.3, Q.sub.6, Q.sub.7 and Q.sub.10. On the other hand, the transistors Q.sub.4 and Q.sub.5 of the first gain control unit 6 and the transistors Q.sub.8 and Q.sub.9 of the second gain control unit 8 are turned OFF, respectively, and thus a high frequency signal voltage is created to the resistors R.sub.5 -R.sub.8.
Therefore, the high frequency signal voltage input from the input terminal 1 and is amplified through the capacitor C.sub.1 by the differential operation of the transistors Q.sub.1 and Q.sub.2 and then amplified by the first gain control unit 6 having a gain controlled to a maximum value by the gain control voltage (V.sub.2 +.DELTA.V) (V) applied to the gain control voltage application terminal 3.
Next, the signal voltage output from the first gain control unit 6 and is amplified through the capacitors C.sub.3 and C.sub.4 by the second gain control unit 8 having a gain controlled to a maximum value by the gain control voltage (V.sub.2 +.DELTA.V) (V) applied to the gain control voltage application terminal 3 and then output from the output terminal 7 through the capacitor C.sub.5.
On the other hand, when the gain of the gain control circuit is reduced (hereinafter, this is referred to as at the time of gain reduction), a voltage (V.sub.2 -.DELTA.V) (V) is applied to the gain control voltage application terminal 3 as a gain control voltage.
With this arrangement, the transistors Q.sub.3 and Q.sub.6 of the first gain control unit 6 and the transistors Q.sub.7 and Q.sub.10 of the second gain control unit 8 are turned OFF, respectively and the collector direct currents I.sub.C3, I.sub.C6, I.sub.C7 and I.sub.C10 flowing to the respective transistors Q.sub.3, Q.sub.6, Q.sub.7 and Q.sub.10 are reduced to a very small amount. On the other hand, the transistors Q.sub.4 and Q.sub.5 of the first gain control unit 6 and the transistors Q.sub.8 and Q.sub.9 of the second gain control unit 8 are turned ON, respectively and collector direct currents I.sub.C4, I.sub.C5, I.sub.C8 and I.sub.C9 flow to the respective transistors Q.sub.4, Q.sub.5, Q.sub.8 and Q.sub.9.
Therefore, the high frequency signal voltage input from the input terminal 1 is amplified through the capacitor C.sub.1 by the differential operations of the transistors Q.sub.1 and Q.sub.2 and attenuated by the first gain control unit 6 having a gain reduced by the gain control voltage (V.sub.2 -.DELTA.V) (V) applied to the gain control voltage application terminal 3.
Next, a small amount of the signal voltage output from the first gain control unit 6 is further attenuated through the capacitors C.sub.3 and C.sub.4 by the second gain control unit 8 having a gain further reduced by the gain control voltage (V.sub.2 -.DELTA.V) (V) applied to the gain control voltage application terminal 3 and then output from the output terminal 7 through the capacitor C.sub.5.
As described above, the signal voltage output from the gain control circuit is kept to a predetermined level by applying a voltages from (V.sub.2 -.DELTA.V) (V) to (V.sub.2 +.DELTA.V) (V) to the gain control voltage application terminal 3 as the gain control voltage in accordance with the high frequency signal voltage output from the output terminal 7.
Incidentally, the aforesaid conventional gain control circuit has a drawback that a large amount of power is consumed because the collector direct currents flow in parallel to the transistors Q.sub.3 -Q.sub.10 at all times.
An object of the present invention made under the above background is to provide a gain control circuit by which a power consumption can be reduced.